Using Design FMEAs to Manage Design Risk(Note: Training offered in both class and workshop format)
The Design Process fails any time a Product Design Specification (i.e. dimension, material property and/or software code) is released to manufacturing that results in a product being built that does not meet one or more of its design requirements. When this happens both the company who designed the product and the end customer are exposed to risk.
Unfortunately, due to the volume of design requirements for a product and the fact that some design requirements may compete, it is often impossible to define Product Design Specifications that define a product that will not fail. Although no design failures are the goal, the Product Design Specifications must be optimized to define a product that does not exceed a failure rate that is acceptable to the customer and the company who designed the product. The Design FMEA and its supporting Design Verification Plan provide a systematic method for accomplishing this task. Using a product of the classes choice, attendees will learn how to use the Design FMEA and Design Verification Plan to “risk optimize” the Product Design Specifications.
Along with the Design FMEA fundamentals, attendees will learn the common mistakes found in 99% of Design FMEAs and how to avoid them. They will also be shown how to spend an average of 15 seconds or less on each Design FMEA rating thus removing one of the most significant ways people waste time when performing Design FMEAs.
The Key role that the Design FMEA and Design Verification Plan play in meeting the risk-based thinking requirements of ISO 9001:2015 and IATF 16949 will be explained.
If material is presented using a multi-day Workshop, the goal is to provide Design FMEA and Design Verification Plan of “Customer Delivery Quality” as well as educate attendees on the fundamentals of their use and creation.
Who Should Attend:
All personnel who are responsible for the creation and maintenance of product designs should attend the class.
Students must have knowledge of the product that they choose to use for the class exercises. If they exist, Requirements Risk Assessment (RRA®), Product Design Requirements documents, prints and bill of materials for product that the Design FMEA and Design Verification Plan will be developed for must be brought to the session.
Class (One Day); Workshop (Two to five Days depending on product complexity).
- The role of the RRA®, Design FMEA, Process FMEA, Design Validation Plan, Design Verification Plan and Process Control Plan in the product development process;
- Linkages between RRA®, Design FMEA, Design FMEA, Process FMEA, Design Validation Plan, Design Verification Plan and Process Control Plan.
How to Perform a Design FMEA:
- Elements of the Design FMEA that can be derived by the Requirements Risk Assessment if one exists;
- Eighteen categories of design requirements that must be considered;
- Typical and special case failure modes;
- Typical and special case effects;
- How to determine Severity (SEV) ratings in two minutes or less;
- Two required elements of a Design FMEA failure cause;
- How to determine Occurrence (OCC) ratings in 15 seconds or less;
- The difference between prevention and detection controls;
- How to determine Detection (DET) ratings in 15 seconds or less;
- How to calculate the Risk Priority Number (RPN) and why it should be rarely used to determine what to work on;
- How to determine class designations in the Design FMEA and their importance in determining what must be worked on;
- Why class designations in the Design FMEA are not transferrable to the Process FMEA;
- The only allowable types of Recommended Actions.
How to Construct a Design Verification Plan
- The purpose of the Design Verification Plan;
- How the Design FMEA can be used to assist in filling out the Design Verification Plan;
- How to use the results of the Design Verification Plan.
- Alternate uses of the information contained in the Design FMEA;
- Obstacles to implementing Design FMEAs and Design Verification Plans effectively.